Fabrication of MOS-transistors

Details Fabrication of MOS-transistors Fabrication of MOS-transistors

1988-04-04

1989-05-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 28, 437 29, 437 41, 437984, H01L 2954, H01L 2900, H01L 2102, H01L 2100

Patent

active

048330973

DESCRIPTION:

BRIEF SUMMARY
This invention relates to a process for the production of transistors and is particularly concerned with the fabrication of shallow p.sup.+ and n.sup.+ doped layers suitable for the sources and drains of submicron CMOS transistors.
Shallow junctions in such transistors have a very high resistance and the aim of the present invention is to reduce the resistance at such junctions.
According to the invention, there is provided a process for the production of a transistor which comprises applying a layer of polysilicon over a gate oxide layer which is surrounded by a field oxide isolation layer located on a suitable substrate; applying a resist layer to the polysilicon layer in a selected region of the latter overlying the gate oxide to define a gate electrode; selective ion implantation to form source and drain regions, said implantation extending through the gate oxide layer to a limited extent except in the region masked by said resist layer; etching away the polysilicon layer and resist layer to leave a gate electrode extending from said oxide layer, activating the source and drain regions and removing the gate oxide in said regions; and finally depositing a conductive layer on the said gate electrode and source and drain regions.
By formation of doped layers to form the source and drain regions by implantation through the polysilicon layer prior to defining the gate electrode, it is possible to achieve shallow p.sup.+ and n.sup.+ doped layers which are suitable for the source and drain regions of submicron CMOS transistors. However, the process according to the invention could also be used in other areas such as, for example, for the production of bipolar transistors.
The source and drain regions may be activated prior to etching away the polysilicon layer to define the gate electrode although it is preferred to activate said regions after the polysilicon layer had been etched away and before the gate oxide layer is removed in the source and drain regions. However, as a further alternative, activation of the dopant layers in the source and drain regions may take place after etching away of the polysilicon layer as well as removal of the gate oxide layer.
The final conductive layer may comprise a silicide or selective refractory metal deposition, e.g. selective tungsten.
The invention also extends to a transistor when made by the above-described process.
The invention will now be further described, by way of example, with reference to the drawings which show successive steps in the production of a transistor according to the invention and in which:
FIG. 1 shows an initial stage in the process according to the invention;
FIG. 2 shows the step of selective ion implantation to form shallow source and drain electrodes in the substrate;
FIG. 3 shows the transistor after etching away of the polysilicon layer;
FIG. 4 shows the transistor after activation of the source and drain regions; and
FIG. 5 shows a completed transistor made by the process according to the invention.
Referring to the drawings, a polysilicon layer 1 is applied over a gate oxide layer 2 which is surrounded by a field oxide isolation layer 3 located on a suitable substrate 4. A resist layer 5 is applied to the polysilicon layer 1 in a selected region of the latter overlying the gate oxide layer 2 to define a gate electrode as shown in FIG. 1.
Selective n type or p type ion implantation is then carried out as shown in FIG. 2, the resist layer 5 acting as a mask so that only selected regions of the substrate underlying the oxide layer 2 are implanted to form the source and drain regions of NMOS or PMOS transistors. The implants 6 and 7 just penetrate through to the active area of the device.
The polysilicon layer 1 is then etched away except in the region underlying the resist layer 5 after which the latter is removed to leave a polysilicon gate 8 as shown in FIG. 3. The source and drain regions 6 and 7 are then activated and diffused to .about.0.1 .mu.m junctions depth to form the structure shown in FIG. 4.
Finally, the gate oxide layer 2 is re

REFERENCES:
patent: 3873373 (1975-03-01), Hill
patent: 4616399 (1986-10-01), Ooka
patent: 4728617 (1988-03-01), Woo et al.
Rideout, V. L., Double Polysilicon Dynamic Random-Access Memory Cell with Increased Charge Storage Capacitance, IBM Tech. Disc. Bull., vol. 21, No. 9, 2/79, pp. 3823-3825.

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