PLL circuit

Details PLL circuit PLL circuit

1998-08-27

2000-11-28

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327147, H03L 706

Patent

active

061540714

ABSTRACT:
In a PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal, a mask circuit controls to transmit or block at least part or all of the phase error signal in accordance with the reference signal or the reproduction signal, an output different from the phase error signal from the phase comparator, and the signal to be compared.

REFERENCES:
patent: 4200845 (1980-04-01), Mendenhall et al.
patent: 5635875 (1997-06-01), Kusakabe
patent: 5712532 (1998-01-01), Ogino
Tsuyama Hioaki, Clock Generating Circuit For Subordinate Synchonizing Network, Patent Abstracts of Japan, vol. 18, No. 549 (E-1618), & JP 06 197101 A (Fujitsu Ltd), Jul. 15, 1994.
Naito Hidefumi, Digital PLL and Synchronizing Separator Circuit, Patent Abstracts of Japan, vol. 097, No. 010 (E-397), Oct. 31, 1997 & JP 09 154037 A (Sony Corp), Jun. 10, 1997.
Takatori Hiroshi, Detection System of Identified Phase, Patent Abstracts of Japan, vol. 10, No. 104 (E-397), Apr. 19, 1986 & JP 60 244130 A (Hitachi Seisakusho KK) Dec. 4, 1985.
Mukumoto Hiroyuki, Digital Phase Locked Loop Circuit, Patent Abstracts of Japan, vol. 012, No. 351 (E-660), Sep. 20, 1988 & JP 63 107231 A (Mitsubishi Electric Corp), May 12, 1988.
Akita Masashi, Digital PLL Circuit, Patent Abstracts of Japan, vol. 13, No. 463 (E-833), Oct. 19, 1989 & JP 01 180118 A (Mitsubishi Electric Corp), Jul. 18, 1989.

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