Integrated test circuit

Details Integrated test circuit Integrated test circuit

1995-06-07

1997-05-20

Nguyen, Hoa T.

Excavating

371 226, 324 731, G01R 3128

Patent

active

056319118

ABSTRACT:
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

REFERENCES:
patent: 4493077 (1985-01-01), Agrawal
patent: 4575674 (1986-03-01), Bass
patent: 4602210 (1986-07-01), Fasang
patent: 4701916 (1987-10-01), Naven
patent: 4745355 (1988-05-01), Eichelberger
Maunder, Boundary Scan, A Framework For Structured Design-For-Test, IEEE International Test Conference 1987 Proceedings, pp. 714-723.

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