Parallel approach to chip wiring

Details Parallel approach to chip wiring Parallel approach to chip wiring

1995-03-07

1997-05-20

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364491, G06F 1750

Patent

active

056318421

ABSTRACT:
In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.

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