Method for fabricating overlaid device in stacked CMOS

Details Method for fabricating overlaid device in stacked CMOS Method for fabricating overlaid device in stacked CMOS

1983-06-17

1985-03-05

O'Keefe, Veronica

Metal working

Method of mechanical manufacture

Assembling or joining

357 239, H01L 21265, H01L 2998, H01L 2100

Patent

active

045022020

ABSTRACT:
In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.

REFERENCES:
patent: 4406710 (1983-09-01), Davies et al.
patent: 4420344 (1983-12-01), Davies et al.
patent: 4434013 (1984-02-01), Bol
A. L. Robinson et al., IEDM, 83, 530-533, 1983.
J. F. Gibbons, IEEE Electron Device Letters, vol. EDL-1, No. 6, pp. 117-118, Jun. 1980.
Jean-Pierre Colinge et al., J. Solid State Circuits, vol. SC-17, No. 2, pp. 215-219, Apr., 1982.
C. E. Chen et al., IEEE Electron Device Letters, vol. EDL-4, No. 8, pp. 272-274, Aug. 1983.
Allied Chemical, Electronic Chem. Prod. Pre. Data Sheet Experimental Boron Spin-on Dopant for Semiconductor Proc, X13150, pp. 1-4.

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