Stacked surrounding wall capacitor

Details Stacked surrounding wall capacitor Stacked surrounding wall capacitor

1990-11-16

1993-08-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437235, 437919, H01L 2170, H01L 2700

Patent

active

052348580

ABSTRACT:
A stacked surrounding wall capacitor (SSWC) using a modified stacked capacitor storage cell fabrication process. The SSWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

REFERENCES:
patent: 5030585 (1991-07-01), Gonzalez et al.
patent: 5100825 (1992-03-01), Fazan et al.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" IEDM, Dig. Tech., Papers, pp. 592-595, 1988 by T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi.
"A Spread Stacked Capacitor (SCC) Cell for 64M Bit DRAMS" IEDM, Dig. Tech. Papers, pp. 31-34, 1989, by S. Inoue, K. Hieda, A. Hitayama, F. Horiguchi and F. Masuoka.

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