Method of manufacturing semiconductor IC using selective poly an

Fishing – trapping – and vermin destroying

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257518, 437 72, 437 99, H01L 21265, H01L 2970

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active

052348458

ABSTRACT:
Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: forming an isolation oxide layer to enclose an active region of a single crystal semiconductor substrate and to have a lower surface than that of the substrate of said active region; simultaneously forming a single crystal silicon layer over the substrate surface of said active region and a polycrystal silicon layer to become integral with said single crystal silicon layer over the surface of said isolation oxide layer by simultaneously growing silicon films over the substrate surface of said active region and the surface of said isolation oxide layer; and forming an active region of a semiconductor element in said single crystal silicon layer.

REFERENCES:
patent: 5008210 (1991-04-01), Chiang et al.
patent: 5061645 (1991-10-01), Nakazato et al.
patent: 5110757 (1992-05-01), Arst et al.
F. Mieno, et al., "Novel Selective Poly-and Epitaxial-Silicon Growth (SPEG) Technique for ULSI Processing", Session 2.2 of IEDM, 1987, pp. 16-19, 1987 IEEE.

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