Dual analog-to-digital converter with single successive approxim

Details Dual analog-to-digital converter with single successive approxim Dual analog-to-digital converter with single successive approxim

1989-02-08

1990-07-10

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, 341158, 341136, H03M 144

Patent

active

049409816

ABSTRACT:
A dual successive approximation analog-to-digital converter, including circuitry for generating separate reference voltages for each analog-to-digital converter, is integrated onto a single semiconductor chip. A single successive approximation register including a 19 bit shift register and two 18 bit latches and associated gating circuitry operates to produce two sets of 18 successive approximation numbers, one supplied as successive digital inputs to a CDAC of one of the analog-to-digital converters and the other set of successive approximation numbers being applied as digital inputs to a CDAC of the other analog-to-digital converter. A CMOS comparator includes two high speed, low gain differential amplifier stages, the first including cascode MOSFETs to provide a high power supply rejection. A pair of auto-zeroing capacitors and a pair of auto-zeroing MOSFETs operate on the outputs of the second differential amplifier to reduce input offset voltage, achieving high speed, low noise operation in a small amount of semiconductor chip area. The auto-zeroed output is supplied to the input of a two stage differential amplifier, the outputs of which also are auto-zeroed and applied to a differential CMOS latch, thereby providing a high speed, low noise, low offset CMOS comparator.

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"A Microelectronic Analog to Digital Converter", by R. Calkins, and M. Hickey, 24th Electronic Components Conference, Washington, U.S.A., pp. 274-278, 13-15 May 1974.

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