Method and apparatus for reducing critical speed path delays

Details Method and apparatus for reducing critical speed path delays Method and apparatus for reducing critical speed path delays

1989-04-27

1990-07-10

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307269, 307480, 307591, 364488, H03K 1901

Patent

active

049409085

ABSTRACT:
A method and apparatus is disclosed for reducing the propagation delay associated with the critical speed path of a binary logic circuit by using "multiplexing logic". More specifically, the inputs to the logic circuit are defined as either critical or non-critical inputs and the product terms are manipulated so that the non-critical inputs are mutually exclusive. The non-critical inputs are supplied to one or more first logic gate structures wherein the ultimate outputs of the first logic gate structures control multiplexer couplers. The critical speed inputs are supplied to one or more second logic gate structures wherein the ultimate outputs of the second logic gate structures are provided as the input to the multiplexer couplers.

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patent: 4700088 (1987-10-01), Tubbs
patent: 4825105 (1989-04-01), Holzle
patent: 4845390 (1989-07-01), Chan
"Compensation for Variation in Circuit Delay", IBM T.D.B., vol. 28, No. 12, May 1986, pp. 5180-5182.

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