Synchronization instruction for multiple processor network

Details Synchronization instruction for multiple processor network Synchronization instruction for multiple processor network

1993-02-19

1994-04-26

Shaw, Gareth D.

Boots, shoes, and leggings

395425, 395650, 395725, 3642304, 364269, 3642712, 364DIG1, G06F 1100

Patent

active

053074831

ABSTRACT:
A computer program synchronization instruction is employed to synchronize multiple processing devices sharing main storage through a common interface. The processors execute the synchronization instruction in turn, and all except the final processor are forced into a temporary holdoff condition and execute no further computer program instructions. The final processor to execute the synchronization program becomes a master, releasing itself and the "slave" devices simultaneously to resume executing instructions. In order to force contentions between processors, a selected delay may be entered into the instruction stream of at least one of the processing devices. The delay can be incremented each time the synchronization instruction is executed, if desired. The forced contentions permit a testing of various serialization mechanisms designed to resolve contentions.

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