Semiconductor memory device including address transition detecti

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518904, 36518905, 36523008, G11C 700

Patent

active

053073240

ABSTRACT:
A transistor is provided for taking written data between a data bus line and a latch circuit in a main amplifier circuit. The gate of the transistor is supplied with a write control signal generated by a write control circuit in writing operation.

REFERENCES:
patent: 4581718 (1986-04-01), Oishi
patent: 4722074 (1988-01-01), Fujishima et al.
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 5065365 (1991-11-01), Hirayama
patent: 5068831 (1991-11-01), Hoshi et al.

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