Semiconductor memory device having improved bit line arrangement

Details Semiconductor memory device having improved bit line arrangement Semiconductor memory device having improved bit line arrangement

1990-03-16

1994-04-26

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365 63, 36518906, 36523001, G11C 1300, G11C 1100

Patent

active

053073070

ABSTRACT:
A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.

REFERENCES:
patent: 4658377 (1987-04-01), McElroy
patent: 4916666 (1990-04-01), Fukuhama et al.
"A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE Journal of Solid-State Circuits, Oct. 1987, vol. SC-22, No. 5, pp. 727-731 by Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, and Shimpei Kayano.

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