Method for optimizing automatic place and route layout for full

Details Method for optimizing automatic place and route layout for full Method for optimizing automatic place and route layout for full

1992-12-10

1994-04-26

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, 3074651, 3073031, H03K 19173

Patent

active

053072863

ABSTRACT:
A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

REFERENCES:
patent: 5029279 (1991-07-01), Sasaki et al.

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