System for specifying addresses by creating a multi-bit ranked o

Details System for specifying addresses by creating a multi-bit ranked o System for specifying addresses by creating a multi-bit ranked o

1994-05-25

1997-03-18

Lee, Thomas C.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

395284, 395412, 34082507, G06F 1310

Patent

active

056131585

ABSTRACT:
An automatic addressing technique for flexibly specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern. The transform elements are passive elements, and no jumpers or settable switches are required to specify the physical addresses when configuring or reconfiguring the system.

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Article by D. Meltzer, entitled "Selective Addressing of Devices Using Primitive Polynomial Transformations" published by IBM Technical Disclosure Bulletin vol. 22, No. 3, Aug. 1979, pp. 1124-1127.

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