Serial register multi-input multiplexing architecture for multip

Details Serial register multi-input multiplexing architecture for multip Serial register multi-input multiplexing architecture for multip

1995-05-19

1997-03-18

Shah, Alpesh M.

Boots, shoes, and leggings

3642322, 3642328, 3642329, 3642384, 364DIG1, G06F 1576

Patent

active

056131445

ABSTRACT:
An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.

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