Translation lookaside buffer that is non-blocking in response to

Details Translation lookaside buffer that is non-blocking in response to Translation lookaside buffer that is non-blocking in response to

1994-09-30

1997-03-18

Lane, Jack A.

395418, G06F 1210

Patent

active

056130830

ABSTRACT:
A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described. An implementation wherein the non-blocking translation lookaside buffer is provided within a microprocessor capable of speculative and out-of-order processing is also described.

REFERENCES:
patent: 5455924 (1995-10-01), Shenoy et al.
Farkas, Keith I. and Norman P. Jouppi. Complexity/Performance Tradeoffs with Non-Blocking Loads. Proceedings of the 21st Annual International Symposium on Computer Architecture. pp. 211-222. Apr. 18-21, 1994.
Popescu, et al., "The Metaflow Architecture," IEEE Micro, pp. 10-13 and 63-73, Jun. 1991.

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