Method of operating a data processor with rapid address comparis

Details Method of operating a data processor with rapid address comparis Method of operating a data processor with rapid address comparis

1995-09-11

1997-03-18

Sheikh, Ayaz R.

395412, G06F 1200

Patent

active

056130813

ABSTRACT:
A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.

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