Semiconductor memory device capable of increasing chip yields wh

Details Semiconductor memory device capable of increasing chip yields wh Semiconductor memory device capable of increasing chip yields wh

1998-07-27

1999-06-22

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 365201, G11C 800, G11C 700

Patent

active

059149078

ABSTRACT:
Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.

REFERENCES:
patent: 5642323 (1997-06-01), Kotani et al.
patent: 5793686 (1998-08-01), Furutani et al.
patent: 5812490 (1998-09-01), Tsukude
"A 1.6GB/s Data-Rate 1 Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", Nitta et al., 1996 IEEE International Solid-State Circuits Conference, 1996 Digest of Technical Papers, pp. 376-377.
"256-Mb DRAM Circuit Technologies for File Applications", Kitsukawa et al., IEEE Journal of Solid-State Circuits vol. 28, No. 11 Nov. 1993, pp. 1105-1112.

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of increasing chip yields wh does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of increasing chip yields wh, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of increasing chip yields wh will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1712632