Congestion based cost factor computing apparatus for integrated

Details Congestion based cost factor computing apparatus for integrated Congestion based cost factor computing apparatus for integrated

1994-04-19

1999-06-22

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

059148870

ABSTRACT:
A cell placement for an integrated circuit chip comprises a large number of cells allocated to respective locations on the surface of the chip. The placement is divided into switch boxes that surround the cell locations respectively. A bounding box is constructed around each net of a netlist for the placement. A congestion factor is computed for each switch box as being equal to the number of bounding boxes that overlap the respective switch box. A cost factor for the placement and associated netlist is computed as the maximum value, average value, sum of squares or other function of the congestion factors. The individual congestion factor computation can be modified to require that a pin of a net of one of the bounding boxes overlap or be within a predetermined distance of a switch box in order for the congestion factor to be computed as the sum of the overlapping bounding boxes in order to localize and increase the accuracy of the cost factor estimation. The congestion factor for a switch box can also be weighted in accordance with the proximity of the switch box to a pin.

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