Multiplex communications – Wide area network – Packet switching
Patent
1991-03-19
1993-12-14
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370106, 3701051, H04J 322
Patent
active
052710068
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a system for transmitting a plurality of low-speed signals having a frame structure within a high-speed frame in multiplex fashion like SONET, or in particular to a frame aligner and a method and system for control suitable for matching the frame phases between the plurality of low-speed signals.
BACKGROUND ART
Conventional systems, as described in Research Applications Report Vol. 28, No. 7, p. 210, Chapter 3.1.1, are known to be of three types including (1) fixed delayed insertion-removal plus frame memory, (2) two-frame memory, and (3) elastic store plus frame memory.
All of these three types of system are such that the phase of writing data into a frame aligner memory (hereinafter referred to as "the frame memory") is compared with the phase of reading the same data, and the approach of one phase to the other is detected thereby to control the writing into the frame memory.
In a system for transmitting low-speed signals having a frame structure within a high-speed frame in multiplex fashion, it is necessary to assure the time sequence (hereinafter referred to as "TSSI", an abbreviation of Time Slot Sequence Integrity) by matching the phases between the low-speed signals arriving from the same channel at the time of terminating the high-speed frame. FIG. 4 shows a case in which the TSSI is assured, and FIG. 5 shows a case in which it is not assured. In FIGS. 4 and 5, there are two types of low-speed frames, A and B. The numerical value in each frame indicates the order of generation of the particular frame. The received frames are aligned in accordance with a predetermined reference phase at the receiving end. Now, assume that the TSSIs of A and B are required to coincide with each other at the receiving end, i.e., that the TSSIs of A and B are required to be assured. In such a case, the reference phase must exist at a place where the order of generation of A coincides with that of B as shown in FIG. 4.
All the conventional systems described above handle only a single frame, so that in terminating the above-mentioned high-speed frames, it is required that each low-speed signal be separated and be subjected to frame alignment individually. As a result, as shown in FIG. 8, in the case where a plurality of low-speed signals to be terminated arrive from a plurality of source stations with the phases thereof distributed over a whole frame, an attempt to assure the TSSI for each of all the source stations would fail as it is impossible to set a reference phase capable of assuring the TSSI for all the source stations.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a frame aligner and a method and system for controlling the same which are capable of executing the frame alignment while assuring the TSSI at the same time.
The above-mentioned object is achieved, according to one aspect of the invention, by setting a plurality of candidates for frame memory write start phase, and providing a memory (hereinafter referred to as "the individual phase memory") for storing a write start phase selected for each low-speed signal stored in a high-speed frame, a memory (hereinafter referred to as "the common phase memory") for storing a write start phase shared by a plurality of low-speed signals among which the TSSI is to be assured, and a memory (hereinafter referred to as "the identification memory") indicating a particular common phase memory that should be referenced.
Also, the above-mentioned object is achieved, according to another aspect of the present invention, by setting a plurality of candidates for frame memory write start phase and providing a memory (hereinafter referred to as "the individual phase memory"), one for each low-speed signal, for storing a write start phase selected for a low-speed signal accommodated in a high-speed frame, a memory (hereinafter referred to as "the reference memory"), one for each low-speed signal, for indicating a particular individual phase memory to be referenced, means for setting
REFERENCES:
patent: 4229815 (1980-10-01), Cummiskey
patent: 4230911 (1980-10-01), Fellinger et al.
patent: 4368531 (1983-01-01), Chopping
patent: 4535446 (1985-08-01), Mountain
patent: 4872073 (1989-10-01), Fincher et al.
patent: 4873684 (1989-10-01), Kobayashi et al.
patent: 4884264 (1989-11-01), Servel et al.
patent: 4905228 (1990-02-01), Angell et al.
patent: 4914655 (1990-04-01), Johannes et al.
patent: 4947388 (1990-08-01), Kuxahara et al.
patent: 5128939 (1992-07-01), Takatori et al.
Ashi Yoshihiro
Kanno Tadayuki
Takatori Masahiro
Ueda Hiromi
Hitachi , Ltd.
Nippon Telegraph and Telephone Corporation
Olms Douglas W.
Ton Dang
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