Semiconductor associative memory device with memory refresh duri

Details Semiconductor associative memory device with memory refresh duri Semiconductor associative memory device with memory refresh duri

1989-01-30

1991-02-05

Hecker, Stuart N.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365188, 365174, 365222, G11C 1500, G11C 1134, G11C 700

Patent

active

049911368

ABSTRACT:
A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first and second n channel MOS transistors constituting a capacitance element. When the word line is activated, a value on the bit line is stored in the first n channel MOS transistor, and the value on the inversion bit line is stored in the second n channel MOS transistor. When the first n channel MOS transistor and the bit line are in the active state, or when the second n channel MOS transistor and the inversion bit line are in the active state, a control terminal is activated. N channel MOS transistors are connected between the control terminal and the first and second n channel MOS transistors, and the first and second n channel MOS transistors are refreshed during matching and reading by means of these transistors.

REFERENCES:
patent: 3701980 (1972-10-01), Mundy
patent: 3705390 (1972-12-01), Mundy
patent: 4646271 (1987-02-01), Uchiyama et al.
patent: 4831585 (1989-05-01), Wade et al.
patent: 4833643 (1989-05-01), Hori
patent: 4862412 (1989-08-01), Fried et al.
patent: 4890260 (1989-12-01), Chuang et al.
Joseph L. Mundy et al., "Low-Cost Associative Memory", IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 364-369.

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