Boots – shoes – and leggings
Patent
1993-03-11
1993-12-14
Malzahn, David H.
Boots, shoes, and leggings
364736, G06F 752
Patent
active
052709620
ABSTRACT:
A multiply and divide circuit having full bit level pipeline capability uses an array of bit level carry-save adders with each carry-save bit adder having a corresponding absolute value bit circuit. In one or two's complement notation, the carry-save adders subtract the binary values supplied thereto and generate an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary numbers supplied thereto. In one mode of operation, the circuit can be used to perform division. In another mode of operation, the circuit can be used to perform multiply and accumulate operation, again with bit level pipeline capability.
REFERENCES:
patent: 4065666 (1977-12-01), Wu
patent: 4550339 (1985-10-01), Fling
patent: 5012439 (1991-04-01), Nash et al.
patent: 5130944 (1992-07-01), Chung et al.
T. E. Williams, M. A. Horowtiz, "A zero-overhead self-timed 160ns 54-b CMOS divider", IEEE Journal Solid State Circuits; 26(11):1651-61, Nov. 1991.
A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, P. G. A. Jespers, "A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor"; IEEE Journal Solid State Circuits, 25(3); 748-56, Jun. 1990.
H. Edamatsu, T. Taniguchi, S. Kuninobu, "A 33 MFLOPS floating point processor using redundant binary representation"; In Proceedings IEEE ISSCC'88, pp. 152-153 and 342-343.
Malzahn David H.
Teknekron Communications Systems, Inc.
LandOfFree
Multiply and divide circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiply and divide circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiply and divide circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1711568