Method of detecting arithmetic or logical computation result

Details Method of detecting arithmetic or logical computation result Method of detecting arithmetic or logical computation result

1992-07-31

1993-12-14

Mai, Tan V.

Boots, shoes, and leggings

364787, G06F 700

Patent

active

052709558

ABSTRACT:
An arithmetic or logical computation result detection circuit is described. The circuit has a set of one-bit-zero cells which receive a first operand, A, a second operand, B, and a C.sub.in, and generates a set of one-bit-zero signals, Z. A combinatorial circuit receives the set of one-bit-zero signals and provides a selected output which is a known function of the one-bit-zero signals. In a preferred embodiment, the combinatorial circuit is a logical AND function which detects a condition when all the one-bit-zero signals are positively asserted. In various embodiments of the preferred invention the one-bit-zero signals may be operable to detect an arithmetic zero condition for operations of addition, subtraction, or a logic operation. Other devices, systems and methods are also disclosed.

REFERENCES:
patent: 4764887 (1988-08-01), Lai et al.
patent: 4815019 (1989-03-01), Bosshart
patent: 4831570 (1989-05-01), Abiko
patent: 4924422 (1990-05-01), Vassiliadis et al.
patent: 5020016 (1991-05-01), Nakano et al.
patent: 5095458 (1992-03-01), Lynch et al.

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