Memory testing apparatus for testing a memory having a plurality

Details Memory testing apparatus for testing a memory having a plurality Memory testing apparatus for testing a memory having a plurality

1996-07-10

1998-11-24

Nguyen, Hoa T.

Excavating

371 271, 371 212, 371 671, 365201, 324765, 3241581, G11C 2900, G01R 3128

Patent

active

058417850

ABSTRACT:
Test results of a memory in which an array of memory cells in the memory is different from a bit array of data read out thereof are written in a failure analysis memory in an array close to the array of the memory cells in the memory. An address scrambler capable of arbitrarily rearranging a bit array of an address signal to be supplied to a memory under test is provided, and an altered address signal a bit array of which is altered by the address scrambler is supplied to a failure analysis memory and the pass/failure judgment results of the memory cells in the memory under test are written in the failure analysis memory at an address space thereof having a structure close to the array structure of the memory cells in the memory under test.

REFERENCES:
patent: 5392294 (1995-02-01), Bosch et al.
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5481671 (1996-01-01), Fujisaki

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