Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Patent
1996-07-16
1998-11-24
Pham, Chi H.
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
370410, 370438, H04J 324
Patent
active
058417745
DESCRIPTION:
BRIEF SUMMARY
This application claims benefit of international application PCT/F195/0012 filed Jan. 13, 1995.
BACKGROUND OF THE INVENTION
The invention relates to a method and system for controlling a statistically multiplexed ATM bus, to the bus being connected a bus controller and interface units for transmission of packets, i.e. cells, over the bus. The invention thus relates to a bus solution applicable to statistical multiplexing and demultiplexing of ATM cells from several interface cards. The interface rates are typically between 0 and 155 Mbit/s.
In an ATM (Asynchronous Transfer Mode), data is transmitted in packets, i.e. cells, of 53 octets. One basic ATM rate at which these cells are transmitted and switched is 155 Mbit/s. When interfaces with a lower transmission rate are connected to an ATM switch that switches 155 Mbit/s cell streams, the ATM cells generated by the interfaces must be multiplexed to this rate. Correspondingly, it must be possible to demultiplex a 155 Mbit/s cell stream to a lower rate.
Previously used bus solutions, such as the SDH multiplexers of product family SYNFONET and the PCM buses of Nokia DX200, are based on time-shared operation of the bus, in which each interface is allocated a separate time slot. This is a waste of bus capacity and is not suitable to statistical multiplexing since bus capacity is assigned irrespective of transmission need. Because of this, concentration, i.e. serving of interfaces having a greater than nominal cell transmission rate, is impossible.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method and system by which the above restrictions can be eliminated. The method of the invention is characterized in that after detecting, for each cell to be transmitted to an ATM bus, the address of the interface unit participating in the transmission, the bus controller sets the address on an address bus of the ATM bus, thereby activating the transmission of the cell from the bus controller to the interface unit, or vice versa, over a data bus of the ATM bus; and that during the transmission of the cell, the bus controller fetches the next interface unit address for transmission of the next cell from or to the interface unit concerned.
The bus allocation in accordance with the invention enables the use of transmission capacity by only those interfaces that have an actual transmission need. The allocation method allows prioritization of interfaces and makes concentration possible by furnishing the bus with interface units having a transmission capacity of above e.g. 155 Mbit/s.
Transmission capacity of a bus controlled as described herein is thus useful in both uplink and downlink directions such that in both directions e.g., a single unit can take the whole transmission capacity if the other units do not have anything to transmit.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, the invention will be described by means of an example with reference to the attached drawing, wherein:
FIG. 1 illustrates the principle of the invention in the multiplexing direction, and
FIG. 2 illustrates the principle of the invention in the demultiplexing direction.
DETAILED DESCRIPTION
The principle of the system shown in FIG. 1 and operating in accordance with the invention is the following.
The ATM bus of the invention is a `point-to-multipoint` type bus with a transmission capacity of e.g., about 155 Mbit/s. Data is transmitted in cells of 53 octets. The start of a cell is indicated by a cell sync pulse, which occurs at 2.72 .mu.s intervals. The bus divides into a multiplexing (`uplink`) element and a demultiplexing (`downlink`) element, the multiplexing element being shown in FIG. 1 and the demultiplexing element being shown in FIG. 2. A multiplexing element 1 of the bus has its own data bus 1d and address bus 1a.
Part 1c of the bus is for timing on the cell and bit level. The operation of the bus is controlled by a bus controller 6, multiplexer, provided with a microprocessor 5 and connected to an ATM switch by a 155 Mbit/s line. The bus fu
REFERENCES:
patent: 4811306 (1989-03-01), Boning et al.
patent: 4896256 (1990-01-01), Roberts
patent: 5237567 (1993-08-01), Nay et al.
patent: 5388229 (1995-02-01), Hyouga et al.
patent: 5402421 (1995-03-01), Tal
patent: 5432782 (1995-07-01), Suzuki
patent: 5446738 (1995-08-01), Kim et al.
Flinck Hannu
Kaukanen Osmo
Seppanen Juha
Ylonen Timo
Nokia Telecommunication Oy
Pham Chi H.
Yao Kwang B.
LandOfFree
Method and system for controlling statistically multiplexed ATM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for controlling statistically multiplexed ATM , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for controlling statistically multiplexed ATM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1711134