Memory system using multiple storage mechanisms to enable storag

Details Memory system using multiple storage mechanisms to enable storag Memory system using multiple storage mechanisms to enable storag

1997-05-29

1998-11-24

Mai, Son

Static information storage and retrieval

Floating gate

Particular connection

365149, 365168, 36518503, G11C 1602, G11C 1156

Patent

active

058416951

ABSTRACT:
A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted. The data sense module is coupled to the first and second data lines, and configured to sense the second charge if the third word line is asserted while the second word line is asserted. The data sense module is further configured to sense the third charge by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module is still further configured to detect the first charge by storing a fourth charge on said second gate if the first word line is asserted while the first data line is de-asserted, the first data line is then asserted, and the first word line is then de-asserted at a predetermined time period after the assertion of the first data line. The fourth charge is then sensed by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module determines the state represented by the stored charge quantities. Since additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

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