System and method for processing graphic delay data of logic cir

Details System and method for processing graphic delay data of logic cir System and method for processing graphic delay data of logic cir

1996-01-30

1998-11-24

Trans, Vincent N.

Boots, shoes, and leggings

364488, 364490, 364491, 364578, G06F 1700, G06F 1750

Patent

active

058416730

ABSTRACT:
A delay network of logic circuit delay data composed of a first set of vertices containing first to fourth vertices, and a first set of weighted directional edges containing a first directional edge extending from the first vertex to the fourth vertex, a second directional edge extending from the second vertex to the third vertex, a third directional edge extending from the first vertex to the third vertex, and a fourth directional edge extending from the second vertex to the fourth vertex, is converted into a delay network composed of a second set of vertices containing the first to fourth vertices and an added fifth vertex, and a second set of weighted directional edges containing a fifth directional edge extending from the first vertex to the fifth vertex, a sixth directional edge extending from the second vertex to the fifth vertex, a seventh directional edge extending from the fifth vertex to the third vertex, and an eighth directional edge extending from the fifth vertex to the fourth vertex.

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patent: 5522063 (1996-05-01), Ashar et al.
patent: 5535145 (1996-07-01), Hathaway

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