Multiplexer circuit and demultiplexer circuit

Details Multiplexer circuit and demultiplexer circuit Multiplexer circuit and demultiplexer circuit

1995-02-27

1997-03-18

Gaffin, Jeffrey A.

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

341100, 370535, 370516, H03M 900

Patent

active

056126956

ABSTRACT:
A counter circuit provides select signals SEL0-SEL3 of a cycle 4Tc sequentially attaining a high level for every 1/4 cycle Tc. A 4-input selector circuit receives data signals I0-I3 of a cycle 4Tc to sequentially output the same for every 1/4 period of Tc in response to a high level of select signals SEL0-SEL3. A flipflop circuit fetches and outputs an output of the selector circuit in synchronization with a clock signal C0. The number of hardware components is reduced in comparison with the conventional case where a select signal generation circuit generates only one select signal SEL, and where a plurality of flipflop circuits and 2-input selector circuits carry out a select and shifting operation of parallel data signals I0-I3.

REFERENCES:
patent: 3961138 (1976-06-01), Fellinger
patent: 4727541 (1988-02-01), Mori et al.
"Multi-Gbits/s Silicon Bipolar Multiplexer And Demultiplexer With Interleaved Architectures", Kevin Negus, Bipolar Circuits and Technology Meeting IEEE 1991, pp. 35-38.

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