Semi-conductor device interconnect package assembly for improved

Details Semi-conductor device interconnect package assembly for improved Semi-conductor device interconnect package assembly for improved

1993-09-24

1995-05-09

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

257737, H01L 2348

Patent

active

054142997

ABSTRACT:
A semiconductor device interconnect package assembly for TAB packages is disclosed having a central portion of material which is utilized as part of the package structure to provide scratch protection to the active surface of a semiconductor die and to the inner lead bonding areas. The central portion of material can be modified in various ways to improve the overall performance of the package, and to reduce stress generated in the TAB package due to thermal mismatch. The assembly also includes a plurality of apertures in the substrate film which overlap and expose a plurality of groups of inner lead portions. The plurality of apertures allows each group of exposed inner lead portions to be encapsulated independently from each other group. By encapsulating each of these groups separately, scratch protection is provided to the inner lead bonding areas while simultaneously reducing the stress on each of the leads due to the heating and cooling of the encapsulating material.

REFERENCES:
patent: 4977441 (1990-12-01), Ohtani et al.
patent: 4994411 (1991-02-01), Naito et al.
patent: 5029325 (1991-07-01), Higgins, III et al.
patent: 5049526 (1991-09-01), McShane et al.
patent: 5075760 (1991-12-01), Nakashima et al.
patent: 5107325 (1992-04-01), Nakayoshi
patent: 5150193 (1992-09-01), Yasuhara et al.
"Stress Analysis of Die Coating for a TAB Application," by Ahmad Hamzehdoost, San Jose, Calif., U.S.A., Jun. 11, 1992.

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