Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-05-23
1999-06-22
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438742, 438738, 438714, 438705, H01L 2100
Patent
active
059142774
ABSTRACT:
The present invention provides a method for forming a metallic wiring pattern, in which narrowing of a resist during patterning of a metallic film is prevented, adhesion of sputtered metallic film to the side walls of the resist is also prevented, and thereby a highly accurate metallic wiring pattern can be achieved. In the method for forming a metallic wiring pattern according to the present invention, a first dry-etching step is performed using a resist 20 patterned in accordance with a wiring pattern as a mask under conditions achieving a ratio sufficiently close to 1 between the etching selectivity for an organic antireflection film 18 and that for a tungsten film 16 such that the etching reaction proceeds in a manner of transcribing the smooth surface of the organic antireflection film 18 while smoothing uneven portions on the surface of the tungsten film 16; and a second dry-etching is performed under conditions achieving a sufficiently high ratio of the etching selectivity for the tungsten film 16 to that for the resist 20 such that the remaining tungsten film 16 is highly accurately etched into a predetermined tungsten wiring pattern 16a while faithfully transcribing the pattern of the resist 20.
REFERENCES:
patent: 5126289 (1992-06-01), Ziger
patent: 5167762 (1992-12-01), Car et al.
Powell William
Sony Corporation
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