Method of manufacturing a DRAM having peripheral circuitry in wh

Details Method of manufacturing a DRAM having peripheral circuitry in wh Method of manufacturing a DRAM having peripheral circuitry in wh

1995-10-31

1997-03-18

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

056122411

ABSTRACT:
A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.

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Wakamiya et al., "Novel Stacked Capacitor Cell for 64 Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70.

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