Three dimensional multichip package methods of fabrication

Details Three dimensional multichip package methods of fabrication Three dimensional multichip package methods of fabrication

1992-10-23

1993-12-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437208, 437225, 437974, 148DIG135, H01L 2160

Patent

active

052702618

ABSTRACT:
A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having high aspect ratio metallized trenches therein extending from a first surface to a second surface thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate. Next the integrated circuit device is affixed to a carrier such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches. Specific details of the fabrication method and the resultant multichip package are set forth.

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