Method for reducing via inductance in an electronic assembly and

Details Method for reducing via inductance in an electronic assembly and Method for reducing via inductance in an electronic assembly and

Filed on

1998-01-28

Date issued

1998-11-24

Examiner

Kincaid, Kristine

Patent Class

Electricity: conductors and insulators

SubClass

Conduits, cables or conductors

SubSubClass

Preformed panel circuit arrangement

Other Related Categories

174260, 174255, 174261, H05K 100

Type

Patent

Status

active

Patent number

058410759

Description

ABSTRACT:
A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

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