Method of making flash memory cell with self-aligned tunnel diel

Details Method of making flash memory cell with self-aligned tunnel diel Method of making flash memory cell with self-aligned tunnel diel

1994-09-12

1995-05-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 44, 437984, H01L 21266

Patent

active

054139465

ABSTRACT:
This invention provides a stacked gate flash memory cell structure and a method for forming the stacked gate flash memory structure. The invention uses a large angle ion implant beam without wafer rotation to form the source and drain regions of the memory cell. A low doped region is formed between an edge of the first gate electrode and an edge of either the source or drain regions. The tunnel dielectric is formed directly above the low doped region. The width of the low doped region is controlled by the angle of the large angle ion implant beam and can be very accurately controlled. The tunnel dielectric is formed independently of the gate dielectric and the thickness of each can be optimized. The tunnel dielectric area can be made very small which improves reliability and reduces the voltage necessary to program and erase the memory cell.

REFERENCES:
patent: 5360751 (1994-11-01), Lee
patent: 5371028 (1994-12-01), Koh

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