Method of fabricating gate electrode in recess

Details Method of fabricating gate electrode in recess Method of fabricating gate electrode in recess

1991-08-15

1993-12-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437133, 437184, 437203, H01L 21265, H01L 2144

Patent

active

052702286

ABSTRACT:
A method of fabricating a field effect transistor in which the gate electrode is formed in a multiple step recess including a first recess located on one level and a second recess located on a lower level. The second, narrower recess is nested in the first, wider recess. The method is initiated by growing a first semiconductor layer of a low etch rate on a semiconductor substrate. Then, a second semiconductor layer of a high etch rate is grown on the first semiconductor layer. A resist film having an opening in a selected location is formed on the second semiconductor layer. Using this resist film as a mask, the semiconductor layers are selectively etched. The gate electrode is formed at the bottom of the multiple step recess created by the etching.

REFERENCES:
patent: 4719498 (1988-01-01), Wada et al.
patent: 4733283 (1988-03-01), Kuroda
patent: 4849368 (1989-07-01), Yamashita et al.
patent: 4927782 (1990-05-01), Davey et al.
patent: 5110765 (1992-05-01), Bilakanti et al.
Igi et al, "High Power and High Efficiency GaAs FET's in C-Band", IEEE MTT International Microwave Symposium Digest, vol. 1, 1988, pp. 1/4-4/4.

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