Semiconductor memory device having a test mode setting circuit

Details Semiconductor memory device having a test mode setting circuit Semiconductor memory device having a test mode setting circuit

1989-01-26

1991-09-24

Smith, Jerry

Excavating

371 214, 365201, G11C 2900

Patent

active

050519956

ABSTRACT:
In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving CAS signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit (1 20) sets a cell plate voltage of a memory cell (1a) approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data "1" can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving WE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit (201). The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit.

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patent: 4860259 (1989-08-01), Tobita
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