Power on coordination system and method for multiple processors

Details Power on coordination system and method for multiple processors Power on coordination system and method for multiple processors

1990-05-25

1991-12-03

Fleming, Michael R.

Boots, shoes, and leggings

3642292, 3642404, 364273, 364269, 3642707, 3642712, 3649484, 364DIG1, 364DIG2, G06F 1100

Patent

active

050704508

ABSTRACT:
A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.

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