Method of simulating a hexagonal array of computer processors an

Details Method of simulating a hexagonal array of computer processors an Method of simulating a hexagonal array of computer processors an

1991-02-08

1991-12-03

Chan, Eddie P.

Boots, shoes, and leggings

3642319, 3642323.DIG.1, G06F 1516, G06F 1576, G06F 1580

Patent

active

050704460

ABSTRACT:
A method is described for simulating a hexagonal array of computer processors or memories in a computer in which the processor and/or memories are physically connected in a rectilinear grid. The grid provides for communication between adjacent processors in both the horizontal and vertical directions. Thus, it provides physical connections between each processor and four nearest neighbor processors. Each processor is provided with two additional nearest neighbor processors by providing communication between each processor of the array and two additional adjacent processors located on different diagonals in the array. As a result of this arrangement the two additional processors are located either in the same column but in different rows adjacent to the row in which the neighboring processor is located or they are in the same row but in different columns adjacent to the column in which the neighboring processor is located. These additional communication patterns for all the processors add to the rectilinear array a zig zag communication pattern running through the array in either the vertical or horizontal direction.

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IEEE Transactions on Computers, vol. C-26, No. 5, "The Indirect Binary n-Cube Microprocessor Array" written by M. Pease, III, May 1977, pp. 458-473.

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