Signal transmission circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307481, 307242, H03K 190175

Patent

active

050702629

ABSTRACT:
A signal transmission circuit (10) for transmitting a signal (V.sub.IN) between dies on a wafer. A transmission node (72) is precharged to a first voltage (70) that is representative of a first of a plurality of bit values in response to the actuation of a gate (48) of a P-channel transistor (50) by a first state control signal (.phi..sub.1). At a later time, a second state of the control signal (.phi..sub.1) actuates a pass gate transistor (38) to couple the end of a first transmission signal line segment (32) to a node (40). A preselected state of the node (40) will cause the signal node (72) to be grounded to a logic zero (74). The signal node (72) is selectively coupled to a latch (92) by a one-shot pass gate (76). The output (102) of the latch (92) is connected to the beginning end of a second transmission line segment (104). The transmission of the signal thus relies on the state of the signal node (72) rather than on the presence or absence of a connection directly to a voltage supply such as V.sub.dd.

REFERENCES:
patent: 3702945 (1972-11-01), Faith et al.
patent: 4769562 (1988-09-01), Ghisio
patent: 4812685 (1989-03-01), Anceau
Bakoglu and Meindl, "CMOS Driver and Driver Circuits for Reduced Interconnection Delays", Proceeding of the Second International Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan (May 1985).
Bakoglu and Meindl, "New CMOS Driver and Receiver Circuits Reduce Interconnection Propagation Delays", Digest of Technical Papers, 1985 Symposium on VLSI Technology, Kobe, Japan, pp. 54-5 (May, 1985).

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