Emergency resumption processing apparatus for an information pro

Details Emergency resumption processing apparatus for an information pro Emergency resumption processing apparatus for an information pro

1990-10-16

1993-07-06

Canney, Vincent P.

Excavating

371 91, G06F 1100

Patent

active

052261514

ABSTRACT:
An emergency resumption processing apparatus for an information processing system includes a program pattern writing part established within a central processing unit, which writing part writes a program pattern that causes a watchdog timer to provide an overflow action in a loading area of the emergency resumption processing program on the main memory device of the information processing system. An emergency resumption processing program loading part established within the same central processing unit reads the emergency resumption processing program from an external memory device after the writing process has been completed, and loads it on the main memory device by rewriting the program pattern written by the program writing part. As a result, if a fault arises in the transmission function of the emergency resumption processing program and the central processing unit starts to run the program on the main memory device without the emergency resumption processing program being loaded on the main memory device, the watchdog timer never becomes accidentally reset and properly detects a system abnormality, since the program pattern written in the main memory device by the program pattern writing part is run.

REFERENCES:
patent: 4371754 (1983-02-01), De et al.
patent: 4377000 (1983-03-01), Staao
patent: 4535404 (1985-08-01), Shenk
IBM Technical Disclosure Bulletin, vol. 28, No. 10, Mar. 1986, p. 4413; `Recovery from an Intermediate Microprocessor Operating State` *the whole document*.
IBM Technical Disclosure Bulletin, vol. 28, No. 1 Jun. 1985, pp. 309-311, `Processor Active Check Scheme`*p. 311, line 27-line 47*.

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