IC testing device for permitting adjustment of timing of a test

Details IC testing device for permitting adjustment of timing of a test IC testing device for permitting adjustment of timing of a test

1991-09-30

1993-07-06

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 324158F, 371 251, G01R 1512, G01R 3102

Patent

active

052257754

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an IC (semiconductor integrated circuit) testing device.
2. Description of the Related Art
An IC testing device comprises, as shown in FIG. 1, a tester main body unit 10 and an IC connection board 81 connected thereto. The IC connection board 81 is called a performance board or test fixture, on which an IC socket 82 is mounted. A plurality of transmission lines L.sub.1 to L.sub.n such as coaxial cables or strip lines are provided which join contacts of the IC socket 82 and junctions of the IC connection board 81 with the testing unit 10. The tester main body 10 and the IC connection board 81 are interconnected by urging pin electrodes provided on one of them against planar electrodes provided on the other, by pressing planar electrodes provided on both of them against each other, or by engaging connectors provided on both of them with each other. An IC to be tested 1 is mounted on the IC socket 82.
A signal generator in the tester main body 10, which is called a formatter, generates a test signal of logical levels at specified timings, based on a pattern and a timing signal. The test signal is converted by a driver in the tester main body 10 into a signal voltage of a predetermined level such as the ECL or TTL level, which is supplied from the tester main body 10 to pins P.sub.1 to P.sub.n of the IC 1 via the transmission lines L.sub.1 to L.sub.n of the IC connection board 81. Then, the resulting IC output response signals derived at the pins P.sub.1 to P.sub.n of the IC 1 are provided via the transmission lines L.sub.1 to L.sub.n of the IC connection board 81 to the tester main body 10, wherein they are compared by a comparator with a reference voltage for the decision of their logical level. Each logical signal based on the decision is compared by a logical comparator in the tester main body 10 with an expected value pattern contained in the test pattern, and the output form the logical comparator is used to determine whether the IC 1 under test is good or bad.
In this instance, it is necessary that the timing for sending out the test signal and the timing for fetching the IC output response signal in the testing main body 10 be determined taking into account not only the relative delay times between respective circuits in the tester main body 10 corresponding to the pins P.sub.1 to P.sub.n of the IC 1 but also delay times T.sub.1 to T.sub.n of the transmission lines L.sub.1 to L.sub.n of the IC connection board 81 which are connected to the pins P.sub.1 to P.sub.n of the IC 1.
Heretofore, there have been proposed the following two methods to adjust the test signal send-out timing and the IC output response signal acquisition timing in accordance with the delay times T.sub.1 to T.sub.n of the transmission lines L.sub.1 to L.sub.n on the IC connection board 81 corresponding to the pins P.sub.1 to P.sub.n of the IC 1.
According to one of the two methods, the transmission lines L.sub.1 to L.sub.n are made equal in length to make the above-mentioned delay times T.sub.1 to T.sub.n (hereinafter referred to also as the delay times T.sub.1 to T.sub.n in the IC connection board 81) constant, and in the tester main body 10, the above-said timing is corrected using data on the constant time. According to the other method, the lengths of the transmission lines L.sub.1 to L.sub.n, i.e. the above-noted delay times T.sub.1 to T.sub.n are measured by a proper method, the measured data are stored in a memory provided in the tester main body 10 and the above-said timing is adjusted using the data read out of the memory.
With the method in which the delay times T.sub.1 to T.sub.n in the IC connection board 81 corresponding to the pins P.sub.1 to P.sub.n of the IC 1 are made constant by the use of the transmission lines L.sub.1 to L.sub.n of the same length and data on the constant time is used to adjust the test signal send-out timing and the IC output response signal acquisition timing in the tester main body 10, the fabrication of the

REFERENCES:
patent: Re31056 (1982-10-01), Chau et al.
patent: 4354268 (1982-10-01), Michel et al.
patent: 4497056 (1985-01-01), Sugamori
patent: 4994732 (1991-02-01), Jeffrey et al.

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