System for handling occurrence of exceptions during execution of

Details System for handling occurrence of exceptions during execution of System for handling occurrence of exceptions during execution of

1989-01-18

1992-07-28

Lee, Thomas C.

Boots, shoes, and leggings

3642286, 3642302, 3642319, 3642628, 36493141, 36493149, 36494831, 3649466, 364DIG1, G06F 928, G06F 930

Patent

active

051346931

ABSTRACT:
A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions include an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means. The exception handler floating-point microinstruction received from the control memory is not stored in the second latching means. The exception handler floating point microinstruction stored in the first latching means is executed. The floating point microinstruction stored in the second latching means is executed. A method for allowing floating point instructions to be executed in a microprocessor in parallel with non-floating point instructions is also described. Circuitry allowing floating point instructions to be executed in parallel with non-floating point instructions is also described.

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"Microprocessor and Peripheral Handbook," vol. 1, pp. 4-1 through 4-165 (Intel Corp. Oct. 1987).

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