Memory device with a phase locked loop circuitry

Details Memory device with a phase locked loop circuitry Memory device with a phase locked loop circuitry

1996-11-15

1997-08-12

Oberley, Alvin E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395552, 36523002, 36523008, 327147, 331 2, G11C 804

Patent

active

056574819

ABSTRACT:
A clock signal generation apparatus for a memory device of a data processing system is described for generating an internal clock signal for the memory device that is synchronized with an external clock signal. The data processing system includes a transmission line for transmitting a global clock signal to the memory device. A first receiving circuit is coupled to a first point of the transmission line for receiving the global clock signal at the first point and for generating a first local clock signal. A first delay circuitry delays the first local clock signal to be a first delayed clock signal such that the first delayed local clock signal is synchronized with the global clock signal received at the first point of the transmission line. The first delay circuitry provides a first variable delay to the first delayed local clock signal. A second receiving circuit is coupled to the second point of the transmission line for receiving the global clock signal at the second point and for generating a second local clock signal. A second delay circuitry delays the second local clock signal to be a second delayed clock signal such that the second delayed local clock signal is synchronized with the global clock signal received at the second point of the transmission line. The second delay circuitry provides a second variable delay to the second delayed local clock signal. A third delay circuitry is coupled to receive the first and second local clock signals for generating the internal clock signal for the memory device at a timing that is halfway between the first and second local clock signals.

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