Trench capacitor DRAM cell and method of manufacture

Details Trench capacitor DRAM cell and method of manufacture Trench capacitor DRAM cell and method of manufacture

1992-01-15

1993-07-06

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437 60, 437919, H01L 2170

Patent

active

052253635

ABSTRACT:
A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

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Jambotkar; IBM TDB, vol. 27, No. 2, Jul. 1984; pp. 1313-1320 shows a memory cell formed in a trench.
Chang et al.; IBM TDB; vol. 22, No. 8B; Jan. 1980; pp. 3683-3688 shows a vertical dRAM cell using either a V-groove or a U-groove.
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Nakajima et al.; IEDM; 1984; pp. 240-243 shows a dRAM cell formed on a mesa of a substrate. The capacitor is formed surrounding the mesa.
"High Density Memory Cell Structure with two Access Transistors", IBM Technical Disclosure Bulletin, pp. 409-414, vol. 31, No. 7, Dec. 1988.

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