Method of forming late isolation with polishing

Details Method of forming late isolation with polishing Method of forming late isolation with polishing

1991-08-23

1993-07-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437 72, 437235, 437236, 148DIG86, H01L 21265

Patent

active

052253589

ABSTRACT:
Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.

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