Superscalar microprocessor having combined register and memory r

Details Superscalar microprocessor having combined register and memory r Superscalar microprocessor having combined register and memory r

1996-12-19

1999-06-08

Maung, Zarni

395561, 39580023, G06F 900

Patent

active

059110570

ABSTRACT:
Circuits, systems, and methods of operating a processor (110) to process a plurality of instructions, wherein each of the plurality of instructions has a respective sequence number. Further, selected ones of the plurality of instructions are for accessing a non-register memory (18). For each of the selected ones of the plurality of instructions, the method comprises the following steps. One step (24) receives the instruction and another (26) decodes the received instruction. Yet another step (30) stores a plurality of instruction characteristics in a table (14), wherein the characteristics include the sequence number of the instruction, an identifier of the non-register memory to be accessed by the instruction, and a correlation identifier of the non-register memory to a physical register.

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ARB: a hardware mechanism for dynamic reordering of memory references by Franklin et al., IEEE publication, vol. 45, No. 5, May 1996, pp. 552-571.

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