Data processing system and method of permutation with replicatio

Details Data processing system and method of permutation with replicatio Data processing system and method of permutation with replicatio

1998-04-17

1999-11-30

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

712 7, 712 4, G06F 9305, G06F 934

Patent

active

059960574

ABSTRACT:
The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary functions within the vector registers.

REFERENCES:
patent: 5553309 (1996-09-01), Asai et al.
patent: 5990821 (1998-08-01), Pflum
Hewlett Packard, "64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture", Computing Directory Technologies Precision Architecture Document, "MIPS Digital Media Extension", Rev 1.0 C-1 through C40 (1997).

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