Method of forming self-aligned contacts in a semiconductor proce

Details Method of forming self-aligned contacts in a semiconductor proce Method of forming self-aligned contacts in a semiconductor proce

1991-01-28

1992-07-28

Quach, T. N.

Fishing, trapping, and vermin destroying

437 31, 437 56, 437200, 437228, 437193, 148DIG19, H01L 21335, H01L 21283

Patent

active

051340836

ABSTRACT:
A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required to the interconnection of the MOS and NPN transistors. Self-aligned interconnects are formed by patterning polysilicon, an insulative layer, And a silicide layer, using first silicide contacts over device components as etch stop.

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