Method of fabricating a semiconductor structure having MOS and b

Details Method of fabricating a semiconductor structure having MOS and b Method of fabricating a semiconductor structure having MOS and b

1991-06-10

1992-07-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437 57, 437 41, 148DIG9, H01L 21265

Patent

active

051340828

ABSTRACT:
A method of fabricating a semiconductor structure having MOS and bipolar devices includes providing an isolation structure having MOS and bipolar active areas including doped wells. A collector region is formed in the bipolar active area well and a first semiconductor layer is then formed over the MOS and bipolar active areas. An active base region is formed in the bipolar active area well and a dielectric layer is formed on the first semiconductor layer over a portion of the bipolar active area. A window is formed through the dielectric layer and extends to the first semiconductor layer. A second semiconductor layer is then formed over the MOS and bipolar active areas. A gate electrode is formed on the MOS active area and emitter and collector electrodes are formed on the bipolar active area. The gate, emitter and collector electrodes are formed from both the first and second semiconductor layers and the emitter electrode extends into the window. After doping the emitter and collector electrodes, self-aligned source and drain regions are diffused into the MOS active area and an emitter region is diffused into the bipolar active area from the emitter electrode through the window.

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