Logic simulator

Details Logic simulator Logic simulator

1997-01-15

1999-06-08

Teska, Kevin J.

Boots, shoes, and leggings

364490, G06F 9455, G06F 1750

Patent

active

059109017

ABSTRACT:
A logic simulator, which is capable of running logic simulations in a short period of time by eliminating operations relating to portions of a logic circuit which have previously been developed. A simulation performing section runs a logic simulation based on a net list and an input test vector, and outputs an output test vector which expresses the results. A macro generating section generates ROM code for a ROM equivalent to the logic circuit being simulated based on the input test vector and the output test vector, and stores this as a ROM macro. When the net list references the ROM macro in subsequent logic simulations, the simulation performing section refers to the ROM code of the ROM macro.

REFERENCES:
patent: 4961156 (1990-10-01), Takasaki
patent: 5051938 (1991-09-01), Hyduke
patent: 5164911 (1992-11-01), Juran et al.
patent: 5177440 (1993-01-01), Walker et al.
patent: 5363319 (1994-11-01), Okuda
patent: 5541861 (1996-07-01), Komoda et al.

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